In the sub-micron era of today's rapidly emerging semiconductor manufacturing industry, gate oxide thicknesses are scaled down to the range of 10-20 angstroms. It is therefore critically essential to maintain gate oxides at their intended thicknesses, since any variation in thickness will be a significant one in such thickness range.
In addition to utilizing reduced gate oxide thicknesses, many semiconductor devices are designed to include two or more gate oxide thicknesses. For example, integrated circuit driver devices typically include high voltage and low voltage regions and use at least three operating voltages. The different operating voltages are used for different device types formed on the substrate and the different operating voltages are associated with gate oxide thicknesses that differ according to the operating voltage. A challenge in semiconductor manufacturing technology is to form multiple gate oxides of various thicknesses on the same substrate, then to define and form associated devices using the various gate oxides, while preserving the integrity of the gate oxides and maintaining correct gate oxide thicknesses by preventing the formation of chemical or other gate oxides during cleaning or other operations.
Wet etching procedures are typically used to remove the gate oxide from exposed areas not covered by photoresist, so that a further gate oxide having a different thickness can be subsequently formed in the exposed areas to produce the multiple gate oxide thickness effect. In some devices, this process may be repeated so that a photoresist pattern is also formed over portions of two different gate oxide thicknesses to remove the oxide from the exposed areas and subsequently form a third gate oxide. It can be appreciated that the oxides must be completely removed from the exposed areas if the subsequently formed gate oxide is to have a desired thickness in the range discussed above.
According to conventional technology for forming multiple gate oxide thicknesses, an oxide is grown, and a photoresist pattern formed over the oxide. The oxide is etched in areas not covered by the photoresist pattern using DHF (dilute HF) or BHF (buffered HF). The photoresist is then stripped using an SPM solution then a two-step, RCA clean using NH3 and H2O2 is used to clean the etched areas prior to the formation of a second, thinner oxide in the exposed areas. Using conventional technology, however, a chemical oxide forms on the silicon surface after the etching operation and during the cleaning operations. The chemical oxide is an oxide that forms on silicon surfaces during wet cleaning and rinsing operations and is highly hydrated, having a composition that differs from stoichiometric SiO2 and may be represented by SiOx, with x<2. Such chemical oxides can undesirably grow to thicknesses of 10 angstroms and greater and this compromises the ability to form gate oxides having targeted thicknesses in the 10-20 angstrom range.
One attempt to subvert the growth of the chemical oxide is to add a final HF process but the addition of an HF-final process carries with it the shortcomings of high particle counts, watermarks formed on the substrate, and organic residue. Another approach is to replace the RCA clean with the SPM cleaning solution, an H2SO4:H2O2 mixture typically in a 1:4 ratio. The use of the SPM solution, however, degrades gate oxide integrity and potentially damages the silicon surface.
As such, there is a need to provide a cleaning operation that addresses the above shortcomings and provides an efficient and fast cleaning method that strips photoresist and cleans an etched surface without the undesirable formation of a thick chemical oxide. The present invention addresses these and other needs.